APM:Libraries
mcuconf.h
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1 /*
2  ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 /*
17  * This file is free software: you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation, either version 3 of the License, or
20  * (at your option) any later version.
21  *
22  * This file is distributed in the hope that it will be useful, but
23  * WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
25  * See the GNU General Public License for more details.
26  *
27  * You should have received a copy of the GNU General Public License along
28  * with this program. If not, see <http://www.gnu.org/licenses/>.
29  *
30  * Modified for use in AP_HAL by Andrew Tridgell and Siddharth Bharat Purohit
31  */
32 /*
33  this provides the default mcuconf.h for each board. Override values in hwdef.dat
34  */
35 // include generated config
36 #include "hwdef.h"
37 
38 #pragma once
39 /*
40  * STM32F4xx drivers configuration.
41  * The following settings override the default settings present in
42  * the various device driver implementation headers.
43  * Note that the settings for each driver only have effect if the whole
44  * driver is enabled in halconf.h.
45  *
46  * IRQ priorities:
47  * 15...0 Lowest...Highest.
48  *
49  * DMA priorities:
50  * 0...3 Lowest...Highest.
51  */
52 
53 /*
54  * HAL driver system settings.
55  */
56 #define STM32_NO_INIT FALSE
57 
58 #ifndef STM32_HSI_ENABLED
59 #define STM32_HSI_ENABLED TRUE
60 #endif
61 
62 #ifndef STM32_LSI_ENABLED
63 #define STM32_LSI_ENABLED TRUE
64 #endif
65 
66 #ifndef STM32_HSE_ENABLED
67 #define STM32_HSE_ENABLED TRUE
68 #endif
69 
70 #ifndef STM32_LSE_ENABLED
71 #define STM32_LSE_ENABLED FALSE
72 #endif
73 
74 #ifndef STM32_CLOCK48_REQUIRED
75 #define STM32_CLOCK48_REQUIRED TRUE
76 #endif
77 
78 #ifndef STM32_SW
79 #define STM32_SW STM32_SW_PLL
80 #endif
81 
82 #ifndef STM32_PLLSRC
83 #define STM32_PLLSRC STM32_PLLSRC_HSE
84 #endif
85 #ifndef STM32_PLLM_VALUE
86 #define STM32_PLLM_VALUE 24
87 #endif
88 #ifndef STM32_PLLN_VALUE
89 #define STM32_PLLN_VALUE 336
90 #endif
91 #ifndef STM32_PLLP_VALUE
92 #define STM32_PLLP_VALUE 2
93 #endif
94 #ifndef STM32_PLLQ_VALUE
95 #define STM32_PLLQ_VALUE 7
96 #endif
97 
98 #define STM32_HPRE STM32_HPRE_DIV1
99 #define STM32_PPRE1 STM32_PPRE1_DIV4
100 #define STM32_PPRE2 STM32_PPRE2_DIV2
101 #define STM32_RTCSEL STM32_RTCSEL_LSI
102 #define STM32_RTCPRE_VALUE 8
103 #define STM32_MCO1SEL STM32_MCO1SEL_HSI
104 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
105 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
106 #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
107 #define STM32_I2SSRC STM32_I2SSRC_CKIN
108 #define STM32_PLLI2SN_VALUE 192
109 #define STM32_PLLI2SR_VALUE 5
110 #define STM32_PVD_ENABLE FALSE
111 #define STM32_PLS STM32_PLS_LEV0
112 #define STM32_BKPRAM_ENABLE FALSE
113 
114 /*
115  * ADC driver system settings.
116  */
117 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
118 #define STM32_ADC_USE_ADC1 TRUE
119 #define STM32_ADC_USE_ADC2 FALSE
120 #define STM32_ADC_USE_ADC3 FALSE
121 #define STM32_ADC_ADC1_DMA_PRIORITY 2
122 #define STM32_ADC_ADC2_DMA_PRIORITY 2
123 #define STM32_ADC_ADC3_DMA_PRIORITY 2
124 #define STM32_ADC_IRQ_PRIORITY 6
125 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
126 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
127 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
128 
129 /*
130  * CAN driver system settings.
131  */
132 #define STM32_CAN_USE_CAN1 FALSE
133 #define STM32_CAN_USE_CAN2 FALSE
134 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
135 #define STM32_CAN_CAN2_IRQ_PRIORITY 11
136 
137 /*
138  * DAC driver system settings.
139  */
140 #define STM32_DAC_DUAL_MODE FALSE
141 #define STM32_DAC_USE_DAC1_CH1 FALSE
142 #define STM32_DAC_USE_DAC1_CH2 FALSE
143 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
144 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
145 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
146 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
147 
148 /*
149  * EXT driver system settings.
150  */
151 #define STM32_EXT_EXTI0_IRQ_PRIORITY 6
152 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6
153 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6
154 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6
155 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6
156 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
157 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
158 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6
159 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15
160 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
161 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
162 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6
163 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15
164 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15
165 
166 /*
167  * GPT driver system settings.
168  */
169 #ifndef STM32_GPT_USE_TIM1
170 #define STM32_GPT_USE_TIM1 FALSE
171 #endif
172 #ifndef STM32_GPT_USE_TIM2
173 #define STM32_GPT_USE_TIM2 FALSE
174 #endif
175 #ifndef STM32_GPT_USE_TIM3
176 #define STM32_GPT_USE_TIM3 FALSE
177 #endif
178 #ifndef STM32_GPT_USE_TIM4
179 #define STM32_GPT_USE_TIM4 FALSE
180 #endif
181 #ifndef STM32_GPT_USE_TIM5
182 #define STM32_GPT_USE_TIM5 FALSE
183 #endif
184 #ifndef STM32_GPT_USE_TIM6
185 #define STM32_GPT_USE_TIM6 FALSE
186 #endif
187 #ifndef STM32_GPT_USE_TIM7
188 #define STM32_GPT_USE_TIM7 FALSE
189 #endif
190 #ifndef STM32_GPT_USE_TIM8
191 #define STM32_GPT_USE_TIM8 FALSE
192 #endif
193 #ifndef STM32_GPT_USE_TIM9
194 #define STM32_GPT_USE_TIM9 FALSE
195 #endif
196 #ifndef STM32_GPT_USE_TIM10
197 #define STM32_GPT_USE_TIM10 FALSE
198 #endif
199 #ifndef STM32_GPT_USE_TIM11
200 #define STM32_GPT_USE_TIM11 FALSE
201 #endif
202 #ifndef STM32_GPT_USE_TIM12
203 #define STM32_GPT_USE_TIM12 FALSE
204 #endif
205 #ifndef STM32_GPT_USE_TIM13
206 #define STM32_GPT_USE_TIM13 FALSE
207 #endif
208 #ifndef STM32_GPT_USE_TIM14
209 #define STM32_GPT_USE_TIM14 FALSE
210 #endif
211 #define STM32_GPT_TIM1_IRQ_PRIORITY 7
212 #define STM32_GPT_TIM2_IRQ_PRIORITY 7
213 #define STM32_GPT_TIM3_IRQ_PRIORITY 7
214 #define STM32_GPT_TIM4_IRQ_PRIORITY 7
215 #define STM32_GPT_TIM5_IRQ_PRIORITY 7
216 #define STM32_GPT_TIM6_IRQ_PRIORITY 7
217 #define STM32_GPT_TIM7_IRQ_PRIORITY 7
218 #define STM32_GPT_TIM8_IRQ_PRIORITY 7
219 #define STM32_GPT_TIM9_IRQ_PRIORITY 7
220 #define STM32_GPT_TIM11_IRQ_PRIORITY 7
221 #define STM32_GPT_TIM12_IRQ_PRIORITY 7
222 #define STM32_GPT_TIM14_IRQ_PRIORITY 7
223 
224 /*
225  * I2C driver system settings.
226  */
227 #define STM32_I2C_BUSY_TIMEOUT 50
228 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
229 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
230 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
231 #define STM32_I2C_I2C1_DMA_PRIORITY 3
232 #define STM32_I2C_I2C2_DMA_PRIORITY 3
233 #define STM32_I2C_I2C3_DMA_PRIORITY 3
234 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
235 
236 /*
237  * I2S driver system settings.
238  */
239 #define STM32_I2S_SPI2_IRQ_PRIORITY 10
240 #define STM32_I2S_SPI3_IRQ_PRIORITY 10
241 #define STM32_I2S_SPI2_DMA_PRIORITY 1
242 #define STM32_I2S_SPI3_DMA_PRIORITY 1
243 #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
244 
245 /*
246  * ICU driver system settings.
247  */
248 #define STM32_ICU_TIM1_IRQ_PRIORITY 7
249 #define STM32_ICU_TIM2_IRQ_PRIORITY 7
250 #define STM32_ICU_TIM3_IRQ_PRIORITY 7
251 #define STM32_ICU_TIM4_IRQ_PRIORITY 7
252 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
253 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
254 #define STM32_ICU_TIM9_IRQ_PRIORITY 7
255 
256 /*
257  * EICU driver system settings.
258  */
259 #define STM32_EICU_TIM1_IRQ_PRIORITY 7
260 #define STM32_EICU_TIM2_IRQ_PRIORITY 7
261 #define STM32_EICU_TIM3_IRQ_PRIORITY 7
262 #define STM32_EICU_TIM4_IRQ_PRIORITY 7
263 #define STM32_EICU_TIM5_IRQ_PRIORITY 7
264 #define STM32_EICU_TIM8_IRQ_PRIORITY 7
265 #define STM32_EICU_TIM9_IRQ_PRIORITY 7
266 #define STM32_EICU_TIM10_IRQ_PRIORITY 7
267 #define STM32_EICU_TIM11_IRQ_PRIORITY 7
268 #define STM32_EICU_TIM12_IRQ_PRIORITY 7
269 #define STM32_EICU_TIM13_IRQ_PRIORITY 7
270 #define STM32_EICU_TIM14_IRQ_PRIORITY 7
271 
272 /*
273  * MAC driver system settings.
274  */
275 #define STM32_MAC_TRANSMIT_BUFFERS 2
276 #define STM32_MAC_RECEIVE_BUFFERS 4
277 #define STM32_MAC_BUFFERS_SIZE 1522
278 #define STM32_MAC_PHY_TIMEOUT 100
279 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
280 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
281 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
282 
283 /*
284  * PWM driver system settings.
285  */
286 #ifndef STM32_PWM_USE_ADVANCED
287 #define STM32_PWM_USE_ADVANCED FALSE
288 #endif
289 #define STM32_PWM_TIM1_IRQ_PRIORITY 7
290 #define STM32_PWM_TIM2_IRQ_PRIORITY 7
291 #define STM32_PWM_TIM3_IRQ_PRIORITY 7
292 #define STM32_PWM_TIM4_IRQ_PRIORITY 7
293 #define STM32_PWM_TIM5_IRQ_PRIORITY 7
294 #define STM32_PWM_TIM8_IRQ_PRIORITY 7
295 #define STM32_PWM_TIM9_IRQ_PRIORITY 7
296 
297 /*
298  * SDC driver system settings.
299  */
300 #define STM32_SDC_SDIO_DMA_PRIORITY 3
301 #define STM32_SDC_SDIO_IRQ_PRIORITY 9
302 #define STM32_SDC_WRITE_TIMEOUT_MS 1000
303 #define STM32_SDC_READ_TIMEOUT_MS 1000
304 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
305 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
306 
307 /*
308  * SERIAL driver system settings.
309  */
310 #define STM32_SERIAL_USART1_PRIORITY 11
311 #define STM32_SERIAL_USART2_PRIORITY 11
312 #define STM32_SERIAL_USART3_PRIORITY 11
313 #define STM32_SERIAL_UART4_PRIORITY 11
314 #define STM32_SERIAL_UART5_PRIORITY 11
315 #define STM32_SERIAL_USART6_PRIORITY 11
316 #define STM32_SERIAL_UART7_PRIORITY 11
317 #define STM32_SERIAL_UART8_PRIORITY 11
318 
319 /*
320  * SPI driver system settings.
321  */
322 #define STM32_SPI_SPI1_DMA_PRIORITY 1
323 #define STM32_SPI_SPI2_DMA_PRIORITY 1
324 #define STM32_SPI_SPI3_DMA_PRIORITY 1
325 #define STM32_SPI_SPI4_DMA_PRIORITY 1
326 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
327 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
328 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
329 #define STM32_SPI_SPI4_IRQ_PRIORITY 10
330 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
331 
332 /*
333  * ST driver system settings.
334  */
335 #define STM32_ST_IRQ_PRIORITY 8
336 #ifndef STM32_ST_USE_TIMER
337 #define STM32_ST_USE_TIMER 2
338 #endif
339 
340 /*
341  * UART driver system settings.
342  */
343 #define STM32_UART_USART1_IRQ_PRIORITY 12
344 #define STM32_UART_USART2_IRQ_PRIORITY 12
345 #define STM32_UART_USART3_IRQ_PRIORITY 12
346 #define STM32_UART_UART4_IRQ_PRIORITY 12
347 #define STM32_UART_UART5_IRQ_PRIORITY 12
348 #define STM32_UART_USART6_IRQ_PRIORITY 12
349 #define STM32_UART_USART1_DMA_PRIORITY 0
350 #define STM32_UART_USART2_DMA_PRIORITY 0
351 #define STM32_UART_USART3_DMA_PRIORITY 0
352 #define STM32_UART_UART4_DMA_PRIORITY 0
353 #define STM32_UART_UART5_DMA_PRIORITY 0
354 #define STM32_UART_USART6_DMA_PRIORITY 0
355 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
356 
357 /*
358  * USB driver system settings.
359  */
360 #ifndef STM32_USB_OTG1_IRQ_PRIORITY
361 #define STM32_USB_OTG1_IRQ_PRIORITY 14
362 #endif
363 #ifndef STM32_USB_OTG2_IRQ_PRIORITY
364 #define STM32_USB_OTG2_IRQ_PRIORITY 14
365 #endif
366 #ifndef STM32_USB_OTG1_RX_FIFO_SIZE
367 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
368 #endif
369 #ifndef STM32_USB_OTG2_RX_FIFO_SIZE
370 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
371 #endif
372 #ifndef STM32_USB_OTG_THREAD_PRIO
373 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO
374 #endif
375 #ifndef STM32_USB_OTG_THREAD_STACK_SIZE
376 #define STM32_USB_OTG_THREAD_STACK_SIZE 128
377 #endif
378 #ifndef STM32_USB_OTGFIFO_FILL_BASEPRI
379 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0
380 #endif
381 
382 /*
383  * WDG driver system settings.
384  */
385 #define STM32_WDG_USE_IWDG FALSE
386 
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