Go to the documentation of this file. 4 #define MPUREG_XG_OFFS_TC 0x00 5 #define MPUREG_YG_OFFS_TC 0x01 6 #define MPUREG_ZG_OFFS_TC 0x02 7 #define MPUREG_X_FINE_GAIN 0x03 8 #define MPUREG_Y_FINE_GAIN 0x04 9 #define MPUREG_Z_FINE_GAIN 0x05 10 #define MPUREG_XA_OFFS_H 0x06 // X axis accelerometer offset (high byte) 11 #define MPUREG_XA_OFFS_L 0x07 // X axis accelerometer offset (low byte) 12 #define MPUREG_YA_OFFS_H 0x08 // Y axis accelerometer offset (high byte) 13 #define MPUREG_YA_OFFS_L 0x09 // Y axis accelerometer offset (low byte) 14 #define MPUREG_ZA_OFFS_H 0x0A // Z axis accelerometer offset (high byte) 15 #define MPUREG_ZA_OFFS_L 0x0B // Z axis accelerometer offset (low byte) 16 #define MPUREG_PRODUCT_ID 0x0C // Product ID Register 17 #define MPUREG_XG_OFFS_USRH 0x13 // X axis gyro offset (high byte) 18 #define MPUREG_XG_OFFS_USRL 0x14 // X axis gyro offset (low byte) 19 #define MPUREG_YG_OFFS_USRH 0x15 // Y axis gyro offset (high byte) 20 #define MPUREG_YG_OFFS_USRL 0x16 // Y axis gyro offset (low byte) 21 #define MPUREG_ZG_OFFS_USRH 0x17 // Z axis gyro offset (high byte) 22 #define MPUREG_ZG_OFFS_USRL 0x18 // Z axis gyro offset (low byte) 23 #define MPUREG_SMPLRT_DIV 0x19 // sample rate. Fsample= 1Khz/(<this value>+1) = 200Hz 24 # define MPUREG_SMPLRT_1000HZ 0x00 25 # define MPUREG_SMPLRT_500HZ 0x01 26 # define MPUREG_SMPLRT_250HZ 0x03 27 # define MPUREG_SMPLRT_200HZ 0x04 28 # define MPUREG_SMPLRT_100HZ 0x09 29 # define MPUREG_SMPLRT_50HZ 0x13 30 #define MPUREG_CONFIG 0x1A 31 # define MPUREG_CONFIG_EXT_SYNC_SHIFT 3 32 # define MPUREG_CONFIG_EXT_SYNC_GX 0x02 33 # define MPUREG_CONFIG_EXT_SYNC_GY 0x03 34 # define MPUREG_CONFIG_EXT_SYNC_GZ 0x04 35 # define MPUREG_CONFIG_EXT_SYNC_AX 0x05 36 # define MPUREG_CONFIG_EXT_SYNC_AY 0x06 37 # define MPUREG_CONFIG_EXT_SYNC_AZ 0x07 38 # define MPUREG_CONFIG_FIFO_MODE_STOP 0x40 39 #define MPUREG_GYRO_CONFIG 0x1B 41 # define BITS_GYRO_FS_250DPS 0x00 42 # define BITS_GYRO_FS_500DPS 0x08 43 # define BITS_GYRO_FS_1000DPS 0x10 44 # define BITS_GYRO_FS_2000DPS 0x18 45 # define BITS_GYRO_FS_MASK 0x18 // only bits 3 and 4 are used for gyro full scale so use this to mask off other bits 46 # define BITS_GYRO_ZGYRO_SELFTEST 0x20 47 # define BITS_GYRO_YGYRO_SELFTEST 0x40 48 # define BITS_GYRO_XGYRO_SELFTEST 0x80 49 #define MPUREG_ACCEL_CONFIG 0x1C 50 #define MPUREG_MOT_THR 0x1F // detection threshold for Motion interrupt generation. Motion is detected when the absolute value of any of the accelerometer measurements exceeds this 51 #define MPUREG_MOT_DUR 0x20 // duration counter threshold for Motion interrupt generation. The duration counter ticks at 1 kHz, therefore MOT_DUR has a unit of 1 LSB = 1 ms 52 #define MPUREG_ZRMOT_THR 0x21 // detection threshold for Zero Motion interrupt generation. 53 #define MPUREG_ZRMOT_DUR 0x22 // duration counter threshold for Zero Motion interrupt generation. The duration counter ticks at 16 Hz, therefore ZRMOT_DUR has a unit of 1 LSB = 64 ms. 54 #define MPUREG_FIFO_EN 0x23 55 # define BIT_TEMP_FIFO_EN 0x80 56 # define BIT_XG_FIFO_EN 0x40 57 # define BIT_YG_FIFO_EN 0x20 58 # define BIT_ZG_FIFO_EN 0x10 59 # define BIT_ACCEL_FIFO_EN 0x08 60 # define BIT_SLV2_FIFO_EN 0x04 61 # define BIT_SLV1_FIFO_EN 0x02 62 # define BIT_SLV0_FIFI_EN0 0x01 63 #define MPUREG_I2C_MST_CTRL 0x24 64 # define BIT_I2C_MST_P_NSR 0x10 65 # define BIT_I2C_MST_CLK_400KHZ 0x0D 66 #define MPUREG_I2C_SLV0_ADDR 0x25 67 #define MPUREG_I2C_SLV1_ADDR 0x28 68 #define MPUREG_I2C_SLV2_ADDR 0x2B 69 #define MPUREG_I2C_SLV3_ADDR 0x2E 70 #define MPUREG_INT_PIN_CFG 0x37 71 # define BIT_BYPASS_EN 0x02 72 # define BIT_INT_RD_CLEAR 0x10 // clear the interrupt when any read occurs 73 # define BIT_LATCH_INT_EN 0x20 // latch data ready pin 74 #define MPUREG_I2C_SLV4_CTRL 0x34 75 #define MPUREG_INT_ENABLE 0x38 77 # define BIT_RAW_RDY_EN 0x01 78 # define BIT_DMP_INT_EN 0x02 // enabling this bit (DMP_INT_EN) also enables RAW_RDY_EN it seems 79 # define BIT_UNKNOWN_INT_EN 0x04 80 # define BIT_I2C_MST_INT_EN 0x08 81 # define BIT_FIFO_OFLOW_EN 0x10 82 # define BIT_ZMOT_EN 0x20 83 # define BIT_MOT_EN 0x40 84 # define BIT_FF_EN 0x80 85 #define MPUREG_INT_STATUS 0x3A 87 # define BIT_RAW_RDY_INT 0x01 88 # define BIT_DMP_INT 0x02 89 # define BIT_UNKNOWN_INT 0x04 90 # define BIT_I2C_MST_INT 0x08 91 # define BIT_FIFO_OFLOW_INT 0x10 92 # define BIT_ZMOT_INT 0x20 93 # define BIT_MOT_INT 0x40 94 # define BIT_FF_INT 0x80 95 #define MPUREG_ACCEL_XOUT_H 0x3B 96 #define MPUREG_ACCEL_XOUT_L 0x3C 97 #define MPUREG_ACCEL_YOUT_H 0x3D 98 #define MPUREG_ACCEL_YOUT_L 0x3E 99 #define MPUREG_ACCEL_ZOUT_H 0x3F 100 #define MPUREG_ACCEL_ZOUT_L 0x40 101 #define MPUREG_TEMP_OUT_H 0x41 102 #define MPUREG_TEMP_OUT_L 0x42 103 #define MPUREG_GYRO_XOUT_H 0x43 104 #define MPUREG_GYRO_XOUT_L 0x44 105 #define MPUREG_GYRO_YOUT_H 0x45 106 #define MPUREG_GYRO_YOUT_L 0x46 107 #define MPUREG_GYRO_ZOUT_H 0x47 108 #define MPUREG_GYRO_ZOUT_L 0x48 109 #define MPUREG_EXT_SENS_DATA_00 0x49 110 #define MPUREG_I2C_SLV0_DO 0x63 111 #define MPUREG_I2C_MST_DELAY_CTRL 0x67 112 # define BIT_I2C_SLV0_DLY_EN 0x01 113 # define BIT_I2C_SLV1_DLY_EN 0x02 114 # define BIT_I2C_SLV2_DLY_EN 0x04 115 # define BIT_I2C_SLV3_DLY_EN 0x08 116 #define MPUREG_USER_CTRL 0x6A 118 # define BIT_USER_CTRL_SIG_COND_RESET 0x01 // resets signal paths and results registers for all sensors (gyros, accel, temp) 119 # define BIT_USER_CTRL_I2C_MST_RESET 0x02 // reset I2C Master (only applicable if I2C_MST_EN bit is set) 120 # define BIT_USER_CTRL_FIFO_RESET 0x04 // Reset (i.e. clear) FIFO buffer 121 # define BIT_USER_CTRL_DMP_RESET 0x08 // Reset DMP 122 # define BIT_USER_CTRL_I2C_IF_DIS 0x10 // Disable primary I2C interface and enable hal.spi->interface 123 # define BIT_USER_CTRL_I2C_MST_EN 0x20 // Enable MPU to act as the I2C Master to external slave sensors 124 # define BIT_USER_CTRL_FIFO_EN 0x40 // Enable FIFO operations 125 # define BIT_USER_CTRL_DMP_EN 0x80 // Enable DMP operations 126 #define MPUREG_PWR_MGMT_1 0x6B 127 # define BIT_PWR_MGMT_1_CLK_INTERNAL 0x00 // clock set to internal 8Mhz oscillator 128 # define BIT_PWR_MGMT_1_CLK_XGYRO 0x01 // PLL with X axis gyroscope reference 129 # define BIT_PWR_MGMT_1_CLK_YGYRO 0x02 // PLL with Y axis gyroscope reference 130 # define BIT_PWR_MGMT_1_CLK_ZGYRO 0x03 // PLL with Z axis gyroscope reference 131 # define BIT_PWR_MGMT_1_CLK_EXT32KHZ 0x04 // PLL with external 32.768kHz reference 132 # define BIT_PWR_MGMT_1_CLK_EXT19MHZ 0x05 // PLL with external 19.2MHz reference 133 # define BIT_PWR_MGMT_1_CLK_STOP 0x07 // Stops the clock and keeps the timing generator in reset 134 # define BIT_PWR_MGMT_1_TEMP_DIS 0x08 // disable temperature sensor 135 # define BIT_PWR_MGMT_1_CYCLE 0x20 // put sensor into cycle mode. cycles between sleep mode and waking up to take a single sample of data from active sensors at a rate determined by LP_WAKE_CTRL 136 # define BIT_PWR_MGMT_1_SLEEP 0x40 // put sensor into low power sleep mode 137 # define BIT_PWR_MGMT_1_DEVICE_RESET 0x80 // reset entire device 138 #define MPUREG_PWR_MGMT_2 0x6C // allows the user to configure the frequency of wake-ups in Accelerometer Only Low Power Mode 139 #define MPUREG_BANK_SEL 0x6D // DMP bank selection register (used to indirectly access DMP registers) 140 #define MPUREG_MEM_START_ADDR 0x6E // DMP memory start address (used to indirectly write to dmp memory) 141 #define MPUREG_MEM_R_W 0x6F // DMP related register 142 #define MPUREG_DMP_CFG_1 0x70 // DMP related register 143 #define MPUREG_DMP_CFG_2 0x71 // DMP related register 144 #define MPUREG_FIFO_COUNTH 0x72 145 #define MPUREG_FIFO_COUNTL 0x73 146 #define MPUREG_FIFO_R_W 0x74 147 #define MPUREG_WHOAMI 0x75 150 #define ICMREG_ACCEL_CONFIG2 0x1D 151 #define ICM_ACC_DLPF_CFG_1046HZ_NOLPF 0x00 152 #define ICM_ACC_DLPF_CFG_218HZ 0x01 153 #define ICM_ACC_DLPF_CFG_99HZ 0x02 154 #define ICM_ACC_DLPF_CFG_44HZ 0x03 155 #define ICM_ACC_DLPF_CFG_21HZ 0x04 156 #define ICM_ACC_DLPF_CFG_10HZ 0x05 157 #define ICM_ACC_DLPF_CFG_5HZ 0x06 158 #define ICM_ACC_DLPF_CFG_420HZ 0x07 159 #define ICM_ACC_FCHOICE_B 0x08 165 #define MPUREG_ICM_UNDOC1 0x11 166 #define MPUREG_ICM_UNDOC1_VALUE 0xc9 169 #define MPU_WHOAMI_6000 0x68 170 #define MPU_WHOAMI_20608 0xaf 171 #define MPU_WHOAMI_20602 0x12 172 #define MPU_WHOAMI_6500 0x70 173 #define MPU_WHOAMI_MPU9250 0x71 174 #define MPU_WHOAMI_MPU9255 0x73 175 #define MPU_WHOAMI_ICM20789 0x03 176 #define MPU_WHOAMI_ICM20789_R1 0x02 177 #define MPU_WHOAMI_ICM20689 0x98 179 #define BIT_READ_FLAG 0x80 180 #define BIT_I2C_SLVX_EN 0x80 183 #define BITS_DLPF_CFG_256HZ_NOLPF2 0x00 184 #define BITS_DLPF_CFG_188HZ 0x01 185 #define BITS_DLPF_CFG_98HZ 0x02 186 #define BITS_DLPF_CFG_42HZ 0x03 187 #define BITS_DLPF_CFG_20HZ 0x04 188 #define BITS_DLPF_CFG_10HZ 0x05 189 #define BITS_DLPF_CFG_5HZ 0x06 190 #define BITS_DLPF_CFG_2100HZ_NOLPF 0x07 191 #define BITS_DLPF_CFG_MASK 0x07 196 #define MPU6000ES_REV_C4 0x14 // 0001 0100 197 #define MPU6000ES_REV_C5 0x15 // 0001 0101 198 #define MPU6000ES_REV_D6 0x16 // 0001 0110 199 #define MPU6000ES_REV_D7 0x17 // 0001 0111 200 #define MPU6000ES_REV_D8 0x18 // 0001 1000 201 #define MPU6000_REV_C4 0x54 // 0101 0100 202 #define MPU6000_REV_C5 0x55 // 0101 0101 203 #define MPU6000_REV_D6 0x56 // 0101 0110 204 #define MPU6000_REV_D7 0x57 // 0101 0111 205 #define MPU6000_REV_D8 0x58 // 0101 1000 206 #define MPU6000_REV_D9 0x59 // 0101 1001 