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Macros
#define	MPU_TYPE_SEPARATED (1U << 0U)

#define	MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U)

#define	MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U)

#define	MPU_CTRL_ENABLE MPU_CTRL_ENABLE_Msk

#define	MPU_CTRL_HFNMIENA MPU_CTRL_HFNMIENA_Msk

#define	MPU_CTRL_PRIVDEFENA MPU_CTRL_PRIVDEFENA_Msk

#define	MPU_RNR_REGION MPU_RNR_REGION_Msk

#define	MPU_RBAR_REGION_MASK MPU_RBAR_REGION_Msk

#define	MPU_RBAR_VALID MPU_RBAR_VALID_Msk

#define	MPU_RBAR_ADDR_MASK MPU_RBAR_ADDR_Msk

#define	MPU_RASR_ENABLE MPU_RASR_ENABLE_Msk

#define	MPU_RASR_SIZE_MASK MPU_RASR_SIZE_Msk

#define	MPU_RASR_SIZE(n) ((n) << MPU_RASR_SIZE_Pos)

#define	MPU_RASR_SIZE_32 MPU_RASR_SIZE(4)

#define	MPU_RASR_SIZE_64 MPU_RASR_SIZE(5)

#define	MPU_RASR_SIZE_128 MPU_RASR_SIZE(6)

#define	MPU_RASR_SIZE_256 MPU_RASR_SIZE(7)

#define	MPU_RASR_SIZE_512 MPU_RASR_SIZE(8)

#define	MPU_RASR_SIZE_1K MPU_RASR_SIZE(9)

#define	MPU_RASR_SIZE_2K MPU_RASR_SIZE(10)

#define	MPU_RASR_SIZE_4K MPU_RASR_SIZE(11)

#define	MPU_RASR_SIZE_8K MPU_RASR_SIZE(12)

#define	MPU_RASR_SIZE_16K MPU_RASR_SIZE(13)

#define	MPU_RASR_SIZE_32K MPU_RASR_SIZE(14)

#define	MPU_RASR_SIZE_64K MPU_RASR_SIZE(15)

#define	MPU_RASR_SIZE_128K MPU_RASR_SIZE(16)

#define	MPU_RASR_SIZE_256K MPU_RASR_SIZE(17)

#define	MPU_RASR_SIZE_512K MPU_RASR_SIZE(18)

#define	MPU_RASR_SIZE_1M MPU_RASR_SIZE(19)

#define	MPU_RASR_SIZE_2M MPU_RASR_SIZE(20)

#define	MPU_RASR_SIZE_4M MPU_RASR_SIZE(21)

#define	MPU_RASR_SIZE_8M MPU_RASR_SIZE(22)

#define	MPU_RASR_SIZE_16M MPU_RASR_SIZE(23)

#define	MPU_RASR_SIZE_32M MPU_RASR_SIZE(24)

#define	MPU_RASR_SIZE_64M MPU_RASR_SIZE(25)

#define	MPU_RASR_SIZE_128M MPU_RASR_SIZE(26)

#define	MPU_RASR_SIZE_256M MPU_RASR_SIZE(27)

#define	MPU_RASR_SIZE_512M MPU_RASR_SIZE(28)

#define	MPU_RASR_SIZE_1G MPU_RASR_SIZE(29)

#define	MPU_RASR_SIZE_2G MPU_RASR_SIZE(30)

#define	MPU_RASR_SIZE_4G MPU_RASR_SIZE(31)

#define	MPU_RASR_SRD_MASK MPU_RASR_SRD_Msk

#define	MPU_RASR_SRD(n) ((n) << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_ALL (0U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB0 (1U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB1 (2U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB2 (4U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB3 (8U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB4 (16U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB5 (32U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB6 (64U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_SRD_DISABLE_SUB7 (128U << MPU_RASR_SRD_Pos)

#define	MPU_RASR_ATTR_B MPU_RASR_B_Msk

#define	MPU_RASR_ATTR_C MPU_RASR_C_Msk

#define	MPU_RASR_ATTR_S MPU_RASR_S_Msk

#define	MPU_RASR_ATTR_TEX_MASK MPU_RASR_TEX_Msk

#define	MPU_RASR_ATTR_TEX(n) ((n) << MPU_RASR_TEX_Pos)

#define	MPU_RASR_ATTR_AP_MASK MPU_RASR_AP_Msk

#define	MPU_RASR_ATTR_AP(n) ((n) << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_XN MPU_RASR_XN_Msk

#define	MPU_RASR_ATTR_AP_NA_NA (0U << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_AP_RW_NA (1U << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_AP_RW_RO (2U << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_AP_RW_RW (3U << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_AP_RO_NA (5U << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_AP_RO_RO (6U << MPU_RASR_AP_Pos)

#define	MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0))

#define	MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) \| MPU_RASR_ATTR_B)

#define	MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) \| MPU_RASR_ATTR_C)

#define	MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) \| MPU_RASR_ATTR_B \| MPU_RASR_ATTR_C)

#define	MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1))

#define	MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) \| MPU_RASR_ATTR_B \| MPU_RASR_ATTR_C)

#define	MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2))

#define	MPU_REGION_0 0

#define	MPU_REGION_1 1

#define	MPU_REGION_2 2

#define	MPU_REGION_3 3

#define	MPU_REGION_4 4

#define	MPU_REGION_5 5

#define	MPU_REGION_6 6

#define	MPU_REGION_7 7

Functions
static void	mpu_enable (uint32_t ctrl)

static void	mpu_disable ()

static void	mpu_configure_region (uint8_t region, uint32_t addr, uint32_t attribs)

Macro Definition Documentation

◆ MPU_CTRL_ENABLE

#define MPU_CTRL_ENABLE MPU_CTRL_ENABLE_Msk

Definition at line 19 of file mpu.h.

Referenced by mpu_enable().

◆ MPU_CTRL_HFNMIENA

#define MPU_CTRL_HFNMIENA MPU_CTRL_HFNMIENA_Msk

Definition at line 20 of file mpu.h.

◆ MPU_CTRL_PRIVDEFENA

#define MPU_CTRL_PRIVDEFENA MPU_CTRL_PRIVDEFENA_Msk

Definition at line 21 of file mpu.h.

Referenced by PendSV_Handler().

◆ MPU_RASR_ATTR_AP

#define MPU_RASR_ATTR_AP ( n ) ((n) << MPU_RASR_AP_Pos)

Definition at line 78 of file mpu.h.

◆ MPU_RASR_ATTR_AP_MASK

#define MPU_RASR_ATTR_AP_MASK MPU_RASR_AP_Msk

Definition at line 77 of file mpu.h.

◆ MPU_RASR_ATTR_AP_NA_NA

#define MPU_RASR_ATTR_AP_NA_NA (0U << MPU_RASR_AP_Pos)

Definition at line 82 of file mpu.h.

◆ MPU_RASR_ATTR_AP_RO_NA

#define MPU_RASR_ATTR_AP_RO_NA (5U << MPU_RASR_AP_Pos)

Definition at line 86 of file mpu.h.

◆ MPU_RASR_ATTR_AP_RO_RO

#define MPU_RASR_ATTR_AP_RO_RO (6U << MPU_RASR_AP_Pos)

Definition at line 87 of file mpu.h.

Referenced by PendSV_Handler().

◆ MPU_RASR_ATTR_AP_RW_NA

#define MPU_RASR_ATTR_AP_RW_NA (1U << MPU_RASR_AP_Pos)

Definition at line 83 of file mpu.h.

◆ MPU_RASR_ATTR_AP_RW_RO

#define MPU_RASR_ATTR_AP_RW_RO (2U << MPU_RASR_AP_Pos)

Definition at line 84 of file mpu.h.

◆ MPU_RASR_ATTR_AP_RW_RW

#define MPU_RASR_ATTR_AP_RW_RW (3U << MPU_RASR_AP_Pos)

Definition at line 85 of file mpu.h.

◆ MPU_RASR_ATTR_B

#define MPU_RASR_ATTR_B MPU_RASR_B_Msk

Definition at line 72 of file mpu.h.

◆ MPU_RASR_ATTR_C

#define MPU_RASR_ATTR_C MPU_RASR_C_Msk

Definition at line 73 of file mpu.h.

◆ MPU_RASR_ATTR_CACHEABLE_WB_NWA

#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)

Definition at line 92 of file mpu.h.

◆ MPU_RASR_ATTR_CACHEABLE_WB_WA

#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C)

Definition at line 94 of file mpu.h.

◆ MPU_RASR_ATTR_CACHEABLE_WT_NWA

#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C)

Definition at line 91 of file mpu.h.

◆ MPU_RASR_ATTR_NON_CACHEABLE

#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1))

Definition at line 93 of file mpu.h.

Referenced by PendSV_Handler().

◆ MPU_RASR_ATTR_NON_SHARED_DEVICE

#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2))

Definition at line 95 of file mpu.h.

◆ MPU_RASR_ATTR_S

#define MPU_RASR_ATTR_S MPU_RASR_S_Msk

Definition at line 74 of file mpu.h.

◆ MPU_RASR_ATTR_SHARED_DEVICE

#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B)

Definition at line 90 of file mpu.h.

◆ MPU_RASR_ATTR_STRONGLY_ORDERED

#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0))

Definition at line 89 of file mpu.h.

◆ MPU_RASR_ATTR_TEX

#define MPU_RASR_ATTR_TEX ( n ) ((n) << MPU_RASR_TEX_Pos)

Definition at line 76 of file mpu.h.

◆ MPU_RASR_ATTR_TEX_MASK

#define MPU_RASR_ATTR_TEX_MASK MPU_RASR_TEX_Msk

Definition at line 75 of file mpu.h.

◆ MPU_RASR_ATTR_XN

#define MPU_RASR_ATTR_XN MPU_RASR_XN_Msk

Definition at line 79 of file mpu.h.

◆ MPU_RASR_ENABLE

#define MPU_RASR_ENABLE MPU_RASR_ENABLE_Msk

Definition at line 29 of file mpu.h.

Referenced by mpu_configure_region().

◆ MPU_RASR_SIZE

#define MPU_RASR_SIZE ( n ) ((n) << MPU_RASR_SIZE_Pos)

Definition at line 31 of file mpu.h.

◆ MPU_RASR_SIZE_128

#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6)

Definition at line 34 of file mpu.h.

◆ MPU_RASR_SIZE_128K

#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16)

Definition at line 44 of file mpu.h.

◆ MPU_RASR_SIZE_128M

#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26)

Definition at line 54 of file mpu.h.

◆ MPU_RASR_SIZE_16K

#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13)

Definition at line 41 of file mpu.h.

◆ MPU_RASR_SIZE_16M

#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23)

Definition at line 51 of file mpu.h.

◆ MPU_RASR_SIZE_1G

#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29)

Definition at line 57 of file mpu.h.

◆ MPU_RASR_SIZE_1K

#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9)

Definition at line 37 of file mpu.h.

◆ MPU_RASR_SIZE_1M

#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19)

Definition at line 47 of file mpu.h.

◆ MPU_RASR_SIZE_256

#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7)

Definition at line 35 of file mpu.h.

◆ MPU_RASR_SIZE_256K

#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17)

Definition at line 45 of file mpu.h.

◆ MPU_RASR_SIZE_256M

#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27)

Definition at line 55 of file mpu.h.

◆ MPU_RASR_SIZE_2G

#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30)

Definition at line 58 of file mpu.h.

◆ MPU_RASR_SIZE_2K

#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10)

Definition at line 38 of file mpu.h.

◆ MPU_RASR_SIZE_2M

#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20)

Definition at line 48 of file mpu.h.

◆ MPU_RASR_SIZE_32

#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4)

Definition at line 32 of file mpu.h.

Referenced by PendSV_Handler().

◆ MPU_RASR_SIZE_32K

#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14)

Definition at line 42 of file mpu.h.

◆ MPU_RASR_SIZE_32M

#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24)

Definition at line 52 of file mpu.h.

◆ MPU_RASR_SIZE_4G

#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31)

Definition at line 59 of file mpu.h.

◆ MPU_RASR_SIZE_4K

#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11)

Definition at line 39 of file mpu.h.

◆ MPU_RASR_SIZE_4M

#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21)

Definition at line 49 of file mpu.h.

◆ MPU_RASR_SIZE_512

#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8)

Definition at line 36 of file mpu.h.

◆ MPU_RASR_SIZE_512K

#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18)

Definition at line 46 of file mpu.h.

◆ MPU_RASR_SIZE_512M

#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28)

Definition at line 56 of file mpu.h.

◆ MPU_RASR_SIZE_64

#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5)

Definition at line 33 of file mpu.h.

◆ MPU_RASR_SIZE_64K

#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15)

Definition at line 43 of file mpu.h.

◆ MPU_RASR_SIZE_64M

#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25)

Definition at line 53 of file mpu.h.

◆ MPU_RASR_SIZE_8K

#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12)

Definition at line 40 of file mpu.h.

◆ MPU_RASR_SIZE_8M

#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22)

Definition at line 50 of file mpu.h.

◆ MPU_RASR_SIZE_MASK

#define MPU_RASR_SIZE_MASK MPU_RASR_SIZE_Msk

Definition at line 30 of file mpu.h.

◆ MPU_RASR_SRD

#define MPU_RASR_SRD ( n ) ((n) << MPU_RASR_SRD_Pos)

Definition at line 61 of file mpu.h.

◆ MPU_RASR_SRD_ALL

#define MPU_RASR_SRD_ALL (0U << MPU_RASR_SRD_Pos)

Definition at line 62 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB0

#define MPU_RASR_SRD_DISABLE_SUB0 (1U << MPU_RASR_SRD_Pos)

Definition at line 63 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB1

#define MPU_RASR_SRD_DISABLE_SUB1 (2U << MPU_RASR_SRD_Pos)

Definition at line 64 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB2

#define MPU_RASR_SRD_DISABLE_SUB2 (4U << MPU_RASR_SRD_Pos)

Definition at line 65 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB3

#define MPU_RASR_SRD_DISABLE_SUB3 (8U << MPU_RASR_SRD_Pos)

Definition at line 66 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB4

#define MPU_RASR_SRD_DISABLE_SUB4 (16U << MPU_RASR_SRD_Pos)

Definition at line 67 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB5

#define MPU_RASR_SRD_DISABLE_SUB5 (32U << MPU_RASR_SRD_Pos)

Definition at line 68 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB6

#define MPU_RASR_SRD_DISABLE_SUB6 (64U << MPU_RASR_SRD_Pos)

Definition at line 69 of file mpu.h.

◆ MPU_RASR_SRD_DISABLE_SUB7

#define MPU_RASR_SRD_DISABLE_SUB7 (128U << MPU_RASR_SRD_Pos)

Definition at line 70 of file mpu.h.

◆ MPU_RASR_SRD_MASK

#define MPU_RASR_SRD_MASK MPU_RASR_SRD_Msk

Definition at line 60 of file mpu.h.

◆ MPU_RBAR_ADDR_MASK

#define MPU_RBAR_ADDR_MASK MPU_RBAR_ADDR_Msk

Definition at line 27 of file mpu.h.

Referenced by mpu_configure_region().

◆ MPU_RBAR_REGION_MASK

#define MPU_RBAR_REGION_MASK MPU_RBAR_REGION_Msk

Definition at line 25 of file mpu.h.

◆ MPU_RBAR_VALID

#define MPU_RBAR_VALID MPU_RBAR_VALID_Msk

Definition at line 26 of file mpu.h.

Referenced by mpu_configure_region().

◆ MPU_REGION_0

#define MPU_REGION_0 0

Definition at line 97 of file mpu.h.

Referenced by PendSV_Handler().

◆ MPU_REGION_1

#define MPU_REGION_1 1

Definition at line 98 of file mpu.h.

◆ MPU_REGION_2

#define MPU_REGION_2 2

Definition at line 99 of file mpu.h.

◆ MPU_REGION_3

#define MPU_REGION_3 3

Definition at line 100 of file mpu.h.

◆ MPU_REGION_4

#define MPU_REGION_4 4

Definition at line 101 of file mpu.h.

◆ MPU_REGION_5

#define MPU_REGION_5 5

Definition at line 102 of file mpu.h.

◆ MPU_REGION_6

#define MPU_REGION_6 6

Definition at line 103 of file mpu.h.

◆ MPU_REGION_7

#define MPU_REGION_7 7

Definition at line 104 of file mpu.h.

◆ MPU_RNR_REGION

#define MPU_RNR_REGION MPU_RNR_REGION_Msk

Definition at line 23 of file mpu.h.

◆ MPU_TYPE_DREGION

#define MPU_TYPE_DREGION ( n ) (((n) >> 8U) & 255U)

Definition at line 16 of file mpu.h.

◆ MPU_TYPE_IREGION

#define MPU_TYPE_IREGION ( n ) (((n) >> 16U) & 255U)

Definition at line 17 of file mpu.h.

◆ MPU_TYPE_SEPARATED

#define MPU_TYPE_SEPARATED (1U << 0U)

Definition at line 15 of file mpu.h.

Function Documentation

◆ mpu_configure_region()

static void mpu_configure_region	(	uint8_t	region,
		uint32_t	addr,
		uint32_t	attribs
	)

inlinestatic

Definition at line 122 of file mpu.h.

Referenced by PendSV_Handler().

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◆ mpu_disable()

static void mpu_disable ( )

inlinestatic

Definition at line 116 of file mpu.h.

Referenced by F4Light::Scheduler::_print_stats(), F4Light::Scheduler::_start_task(), F4Light::Scheduler::get_next_task(), F4Light::Scheduler::resume_boost(), and F4Light::Scheduler::task_resume().

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◆ mpu_enable()

static void mpu_enable ( uint32_t ctrl )

inlinestatic

Definition at line 111 of file mpu.h.

Referenced by PendSV_Handler().

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Macros

Functions

Macro Definition Documentation

◆ MPU_CTRL_ENABLE

◆ MPU_CTRL_HFNMIENA

◆ MPU_CTRL_PRIVDEFENA

◆ MPU_RASR_ATTR_AP

◆ MPU_RASR_ATTR_AP_MASK

◆ MPU_RASR_ATTR_AP_NA_NA

◆ MPU_RASR_ATTR_AP_RO_NA

◆ MPU_RASR_ATTR_AP_RO_RO

◆ MPU_RASR_ATTR_AP_RW_NA

◆ MPU_RASR_ATTR_AP_RW_RO

◆ MPU_RASR_ATTR_AP_RW_RW

◆ MPU_RASR_ATTR_B

◆ MPU_RASR_ATTR_C

◆ MPU_RASR_ATTR_CACHEABLE_WB_NWA

◆ MPU_RASR_ATTR_CACHEABLE_WB_WA

◆ MPU_RASR_ATTR_CACHEABLE_WT_NWA

◆ MPU_RASR_ATTR_NON_CACHEABLE

◆ MPU_RASR_ATTR_NON_SHARED_DEVICE

◆ MPU_RASR_ATTR_S

◆ MPU_RASR_ATTR_SHARED_DEVICE

◆ MPU_RASR_ATTR_STRONGLY_ORDERED

◆ MPU_RASR_ATTR_TEX

◆ MPU_RASR_ATTR_TEX_MASK

◆ MPU_RASR_ATTR_XN

◆ MPU_RASR_ENABLE

◆ MPU_RASR_SIZE

◆ MPU_RASR_SIZE_128

◆ MPU_RASR_SIZE_128K

◆ MPU_RASR_SIZE_128M

◆ MPU_RASR_SIZE_16K

◆ MPU_RASR_SIZE_16M

◆ MPU_RASR_SIZE_1G

◆ MPU_RASR_SIZE_1K

◆ MPU_RASR_SIZE_1M

◆ MPU_RASR_SIZE_256

◆ MPU_RASR_SIZE_256K

◆ MPU_RASR_SIZE_256M

◆ MPU_RASR_SIZE_2G

◆ MPU_RASR_SIZE_2K

◆ MPU_RASR_SIZE_2M

◆ MPU_RASR_SIZE_32

◆ MPU_RASR_SIZE_32K

◆ MPU_RASR_SIZE_32M

◆ MPU_RASR_SIZE_4G

◆ MPU_RASR_SIZE_4K

◆ MPU_RASR_SIZE_4M

◆ MPU_RASR_SIZE_512

◆ MPU_RASR_SIZE_512K

◆ MPU_RASR_SIZE_512M

◆ MPU_RASR_SIZE_64

◆ MPU_RASR_SIZE_64K

◆ MPU_RASR_SIZE_64M

◆ MPU_RASR_SIZE_8K

◆ MPU_RASR_SIZE_8M

◆ MPU_RASR_SIZE_MASK

◆ MPU_RASR_SRD

◆ MPU_RASR_SRD_ALL

◆ MPU_RASR_SRD_DISABLE_SUB0

◆ MPU_RASR_SRD_DISABLE_SUB1

◆ MPU_RASR_SRD_DISABLE_SUB2

◆ MPU_RASR_SRD_DISABLE_SUB3

◆ MPU_RASR_SRD_DISABLE_SUB4

◆ MPU_RASR_SRD_DISABLE_SUB5

◆ MPU_RASR_SRD_DISABLE_SUB6

◆ MPU_RASR_SRD_DISABLE_SUB7

◆ MPU_RASR_SRD_MASK

◆ MPU_RBAR_ADDR_MASK

◆ MPU_RBAR_REGION_MASK

◆ MPU_RBAR_VALID

◆ MPU_REGION_0

◆ MPU_REGION_1

◆ MPU_REGION_2

◆ MPU_REGION_3

◆ MPU_REGION_4

◆ MPU_REGION_5

◆ MPU_REGION_6

◆ MPU_REGION_7