24 #if CONFIG_HAL_BOARD == HAL_BOARD_LINUX 28 #ifndef LSM303D_DRDY_M_PIN 29 #define LSM303D_DRDY_M_PIN -1 33 #define DIR_READ (1<<7) 34 #define DIR_WRITE (0<<7) 35 #define ADDR_INCREMENT (1<<6) 38 #define ADDR_WHO_AM_I 0x0F 41 #define ADDR_OUT_TEMP_L 0x05 42 #define ADDR_OUT_TEMP_H 0x06 43 #define ADDR_STATUS_M 0x07 44 #define ADDR_OUT_X_L_M 0x08 45 #define ADDR_OUT_X_H_M 0x09 46 #define ADDR_OUT_Y_L_M 0x0A 47 #define ADDR_OUT_Y_H_M 0x0B 48 #define ADDR_OUT_Z_L_M 0x0C 49 #define ADDR_OUT_Z_H_M 0x0D 51 #define ADDR_INT_CTRL_M 0x12 52 #define ADDR_INT_SRC_M 0x13 53 #define ADDR_REFERENCE_X 0x1c 54 #define ADDR_REFERENCE_Y 0x1d 55 #define ADDR_REFERENCE_Z 0x1e 57 #define ADDR_STATUS_A 0x27 58 #define ADDR_OUT_X_L_A 0x28 59 #define ADDR_OUT_X_H_A 0x29 60 #define ADDR_OUT_Y_L_A 0x2A 61 #define ADDR_OUT_Y_H_A 0x2B 62 #define ADDR_OUT_Z_L_A 0x2C 63 #define ADDR_OUT_Z_H_A 0x2D 65 #define ADDR_CTRL_REG0 0x1F 66 #define ADDR_CTRL_REG1 0x20 67 #define ADDR_CTRL_REG2 0x21 68 #define ADDR_CTRL_REG3 0x22 69 #define ADDR_CTRL_REG4 0x23 70 #define ADDR_CTRL_REG5 0x24 71 #define ADDR_CTRL_REG6 0x25 72 #define ADDR_CTRL_REG7 0x26 74 #define ADDR_FIFO_CTRL 0x2e 75 #define ADDR_FIFO_SRC 0x2f 77 #define ADDR_IG_CFG1 0x30 78 #define ADDR_IG_SRC1 0x31 79 #define ADDR_IG_THS1 0x32 80 #define ADDR_IG_DUR1 0x33 81 #define ADDR_IG_CFG2 0x34 82 #define ADDR_IG_SRC2 0x35 83 #define ADDR_IG_THS2 0x36 84 #define ADDR_IG_DUR2 0x37 85 #define ADDR_CLICK_CFG 0x38 86 #define ADDR_CLICK_SRC 0x39 87 #define ADDR_CLICK_THS 0x3a 88 #define ADDR_TIME_LIMIT 0x3b 89 #define ADDR_TIME_LATENCY 0x3c 90 #define ADDR_TIME_WINDOW 0x3d 91 #define ADDR_ACT_THS 0x3e 92 #define ADDR_ACT_DUR 0x3f 94 #define REG1_RATE_BITS_A ((1<<7) | (1<<6) | (1<<5) | (1<<4)) 95 #define REG1_POWERDOWN_A ((0<<7) | (0<<6) | (0<<5) | (0<<4)) 96 #define REG1_RATE_3_125HZ_A ((0<<7) | (0<<6) | (0<<5) | (1<<4)) 97 #define REG1_RATE_6_25HZ_A ((0<<7) | (0<<6) | (1<<5) | (0<<4)) 98 #define REG1_RATE_12_5HZ_A ((0<<7) | (0<<6) | (1<<5) | (1<<4)) 99 #define REG1_RATE_25HZ_A ((0<<7) | (1<<6) | (0<<5) | (0<<4)) 100 #define REG1_RATE_50HZ_A ((0<<7) | (1<<6) | (0<<5) | (1<<4)) 101 #define REG1_RATE_100HZ_A ((0<<7) | (1<<6) | (1<<5) | (0<<4)) 102 #define REG1_RATE_200HZ_A ((0<<7) | (1<<6) | (1<<5) | (1<<4)) 103 #define REG1_RATE_400HZ_A ((1<<7) | (0<<6) | (0<<5) | (0<<4)) 104 #define REG1_RATE_800HZ_A ((1<<7) | (0<<6) | (0<<5) | (1<<4)) 105 #define REG1_RATE_1600HZ_A ((1<<7) | (0<<6) | (1<<5) | (0<<4)) 107 #define REG1_BDU_UPDATE (1<<3) 108 #define REG1_Z_ENABLE_A (1<<2) 109 #define REG1_Y_ENABLE_A (1<<1) 110 #define REG1_X_ENABLE_A (1<<0) 112 #define REG2_ANTIALIAS_FILTER_BW_BITS_A ((1<<7) | (1<<6)) 113 #define REG2_AA_FILTER_BW_773HZ_A ((0<<7) | (0<<6)) 114 #define REG2_AA_FILTER_BW_194HZ_A ((0<<7) | (1<<6)) 115 #define REG2_AA_FILTER_BW_362HZ_A ((1<<7) | (0<<6)) 116 #define REG2_AA_FILTER_BW_50HZ_A ((1<<7) | (1<<6)) 118 #define REG2_FULL_SCALE_BITS_A ((1<<5) | (1<<4) | (1<<3)) 119 #define REG2_FULL_SCALE_2G_A ((0<<5) | (0<<4) | (0<<3)) 120 #define REG2_FULL_SCALE_4G_A ((0<<5) | (0<<4) | (1<<3)) 121 #define REG2_FULL_SCALE_6G_A ((0<<5) | (1<<4) | (0<<3)) 122 #define REG2_FULL_SCALE_8G_A ((0<<5) | (1<<4) | (1<<3)) 123 #define REG2_FULL_SCALE_16G_A ((1<<5) | (0<<4) | (0<<3)) 125 #define REG5_ENABLE_T (1<<7) 127 #define REG5_RES_HIGH_M ((1<<6) | (1<<5)) 128 #define REG5_RES_LOW_M ((0<<6) | (0<<5)) 130 #define REG5_RATE_BITS_M ((1<<4) | (1<<3) | (1<<2)) 131 #define REG5_RATE_3_125HZ_M ((0<<4) | (0<<3) | (0<<2)) 132 #define REG5_RATE_6_25HZ_M ((0<<4) | (0<<3) | (1<<2)) 133 #define REG5_RATE_12_5HZ_M ((0<<4) | (1<<3) | (0<<2)) 134 #define REG5_RATE_25HZ_M ((0<<4) | (1<<3) | (1<<2)) 135 #define REG5_RATE_50HZ_M ((1<<4) | (0<<3) | (0<<2)) 136 #define REG5_RATE_100HZ_M ((1<<4) | (0<<3) | (1<<2)) 137 #define REG5_RATE_DO_NOT_USE_M ((1<<4) | (1<<3) | (0<<2)) 139 #define REG6_FULL_SCALE_BITS_M ((1<<6) | (1<<5)) 140 #define REG6_FULL_SCALE_2GA_M ((0<<6) | (0<<5)) 141 #define REG6_FULL_SCALE_4GA_M ((0<<6) | (1<<5)) 142 #define REG6_FULL_SCALE_8GA_M ((1<<6) | (0<<5)) 143 #define REG6_FULL_SCALE_12GA_M ((1<<6) | (1<<5)) 145 #define REG7_CONT_MODE_M ((0<<1) | (0<<0)) 147 #define INT_CTRL_M 0x12 148 #define INT_SRC_M 0x13 150 #define LSM303D_MAG_DEFAULT_RANGE_GA 2 151 #define LSM303D_MAG_DEFAULT_RATE 100 155 , _dev(
std::move(dev))
167 if (!sensor || !sensor->
init(rotation)) {
227 hal.
console->
printf(
"LSM303D _read_data_transaction_accel: _reg7_expected unexpected\n");
240 if ((rx.status & 0x70) != 0) {
244 if (rx.x == 0 && rx.y == 0 && rx.z == 0) {
296 hal.
console->
printf(
"LSM303D: unexpected WHOAMI 0x%x\n", (
unsigned)whoami);
301 for (tries = 0; tries < 5; tries++) {
415 float new_scale_ga_digit = 0.0f;
424 new_scale_ga_digit = 0.080f;
425 }
else if (max_ga <= 4) {
428 new_scale_ga_digit = 0.160f;
429 }
else if (max_ga <= 8) {
432 new_scale_ga_digit = 0.320f;
433 }
else if (max_ga <= 12) {
436 new_scale_ga_digit = 0.479f;
452 if (frequency == 0) {
456 if (frequency <= 25) {
459 }
else if (frequency <= 50) {
462 }
else if (frequency <= 100) {
#define REG6_FULL_SCALE_12GA_M
AP_HAL::OwnPtr< AP_HAL::Device > _dev
Vector3< float > Vector3f
static AP_Compass_Backend * probe(Compass &compass, AP_HAL::OwnPtr< AP_HAL::Device > dev, enum Rotation=ROTATION_NONE)
virtual PeriodicHandle register_periodic_callback(uint32_t period_usec, PeriodicCb)=0
uint8_t _compass_instance
AP_HAL::UARTDriver * console
uint32_t get_bus_id(void) const
void _register_write(uint8_t reg, uint8_t val)
uint8_t _register_read(uint8_t reg)
virtual AP_HAL::Semaphore * get_semaphore()=0
void rotate_field(Vector3f &mag, uint8_t instance)
void publish_filtered_field(const Vector3f &mag, uint8_t instance)
#define REG6_FULL_SCALE_4GA_M
void correct_field(Vector3f &mag, uint8_t i)
#define HAL_SEMAPHORE_BLOCK_FOREVER
#define REG5_RATE_100HZ_M
virtual bool take(uint32_t timeout_ms) WARN_IF_UNUSED=0
AP_Compass_LSM303D(Compass &compass, AP_HAL::OwnPtr< AP_HAL::Device > dev)
#define REG6_FULL_SCALE_8GA_M
#define LSM303D_MAG_DEFAULT_RANGE_GA
void set_dev_id(uint8_t instance, uint32_t dev_id)
virtual void mode(uint8_t output)=0
virtual void delay(uint16_t ms)=0
void _register_modify(uint8_t reg, uint8_t clearbits, uint8_t setbits)
void set_device_type(uint8_t devtype)
bool _mag_set_samplerate(uint16_t frequency)
virtual void printf(const char *,...) FMT_PRINTF(2
bool _block_read(uint8_t reg, uint8_t *buf, uint32_t size)
virtual bool take_nonblocking() WARN_IF_UNUSED=0
static AP_HAL::OwnPtr< AP_HAL::Device > dev
uint8_t register_compass(void) const
virtual bool set_speed(Speed speed)=0
virtual AP_HAL::DigitalSource * channel(uint16_t n)=0
#define REG6_FULL_SCALE_2GA_M
#define LSM303D_DRDY_M_PIN
bool init(enum Rotation rotation)
#define LSM303D_MAG_DEFAULT_RATE
void set_rotation(uint8_t instance, enum Rotation rotation)
AP_HAL::DigitalSource * _drdy_pin_m
bool read_registers(uint8_t first_reg, uint8_t *recv, uint32_t recv_len)
#define FUNCTOR_BIND_MEMBER(func, rettype,...)
void publish_raw_field(const Vector3f &mag, uint8_t instance)
#define REG6_FULL_SCALE_BITS_M
void panic(const char *errormsg,...) FMT_PRINTF(1
bool write_register(uint8_t reg, uint8_t val, bool checked=false)
AP_HAL::Scheduler * scheduler
bool _mag_set_range(uint8_t max_ga)